A relatively modern technology in computer related memory is dual bit memory, which allows multiple bits to be stored in a single cell. In this technology, a memory cell is essentially split into two identical (mirrored) parts, each of which is formulated for storing one of two independent bits. Each dual bit memory cell, like a traditional cell, has a gate with a source and a drain. However, unlike a traditional stacked gate cell in which the source is always connected to an electrical source and the drain is always connected to an electrical drain, respective dual bit memory cells can have the connections of the source and drain reversed during operation to permit the storing of two bits.
One arrangement that facilitates dual bit technology is a SONOS type architecture where a substrate, typically composed of silicon, generally has a layer of silicon oxide, a layer of silicon nitride, a layer of silicon oxide and finally a layer of conductive material (e.g., poly-silicon) formed there-over. Given the electrical properties of the nitride layer, charges trapped within the dual bit memory cell do not readily delocalize, and thus more than one bit can be stored within respective memory cells. The oxide-nitride-oxide (ONO) layers are thus together commonly referred to as a charge trapping dielectric layer.
Bitlines are implanted within the substrate under the charge trapping dielectric layer, and wordlines are formed over the charge trapping dielectric layer substantially perpendicular to the bitlines. In particular, the wordlines may be formed out of the layer of conductive material formed over the charge trapping dielectric ONO layer. Programming circuitry controls two bits per cell by applying a signal to the wordline, which acts as a control gate, and changing bitline connections such that one bit is stored by the source and drain being connected in one arrangement and a complementary bit is stored by the source and drain being interchanged in another arrangement.
Nevertheless, there is an ongoing desire to scale down semiconductor devices and to pack more devices having greater capabilities onto smaller and smaller areas. As device sizes and features are scaled down, however, certain disadvantageous issues can arise. By way of example, forming bitlines closer together shortens the length of respective channels defined there-between, which can lead to complementary bit disturb (CBD), among other things. For example, charge or bit isolation between the two bits stored in the charge trapping layer becomes increasingly difficult as the channel length is decreased and the bits are brought closer together. In this manner, the bits can contaminate one another and operations performed on one bit can affect the other bit. For instance, when one bit is programmed (e.g., to 1 unit of charge) the other (complementary) bit may also (unintentionally) receive a (slight) charge (e.g., to 0.5 units of charge). The charge on the un-programmed bit may make it difficult to isolate or differentiate between the two bits when performing a read operation of the charged bit, for example. Thus, it can be said that a window for reading the programmed cell is decreased, or rather that there is a decrease in a reading margin. In addition, short channel effects and leakage currents as well as other undesirable performance issues can also result scaling and shortened channel lengths.
Similarly, unwanted source/drain leakage conduction or punchthrough current can occur as channel lengths shorten. Punchthrough current may be seen as a parasitic current path existing between the drain and source, which the gate has difficulty in controlling since the current path is located deep in the bulk (substrate) far away from the gate. The actual amount of punchthrough current depends mainly upon the potential distribution under the channel and on the source/drain junction depths. As the effective channel length gets shorter, the source/drain depletion regions get closer together causing this leakage current component to increase. Accordingly, it would be desirable to reduce feature sizes so as to increase packing density while mitigating adverse affects that may result therefrom.